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ECL Pro(R) Micrel
3.3V/5V 2.5GHz PROGRAMMABLE DELAY CHIP
SY100EP195V ECL Pro(R) SY100EP195V
FEATURES
s Pin-for-pin, plug-in compatible to the ON Semiconductor MC100EP195 s Maximum frequency > 2.5GHz s Programmable range: 2.2ns to 12.2ns s 10ps increments s PECL mode operating range: VCC = 3.0V to 5.5V with VEE = 0V s NECL mode operating range: VCC = 0V with VEE = -3.0V to -5.5V s Open input default state s Safety clamp on inputs s A logic high on the /EN pin will force Q to logic low s D[0:10] can accept either ECL, CMOS, or TTL inputs s VBB output reference voltage s Available in a 32-pin TQFP package ECL Pro(R)
DESCRIPTION
The SY100EP195V is a programmable delay line, varying the time a logic signal takes to traverse from IN to Q. This delay can vary from about 2.2ns to about 12.2ns. The input can be PECL, LVPECL, NECL, or LVNECL. The delay varies in discrete steps based on a control word presented to SY100EP195V. The 10-bit width of this latched control register allows for delay increments of approximately 10ps. An eleventh control bit allows the cascading of multiple SY100EP195V devices, for a wider delay range. Each additional SY100EP195V effectively doubles the delay range available. For maximum flexibility, the control register interface accepts CMOS or TTL level signals, as well as the input level at the IN pins. All support documentation can be found on Micrel's web site at www.micrel.com.
APPLICATIONS
s Clock de-skewing s Timing adjustment s Aperture centering
CROSS REFERENCE TABLE
Micrel Semiconductor SY100EP195VTI SY100EP195VTITR ON Semiconductor MC100EP195FA MC100EP195FAR2
TYPICAL APPLICATIONS CIRCUIT
TYPICAL PERFORMANCE
Data Signal of Unknown Phase CLOCK+ CLOCK- SY100EP195V IN Q /IN D[9:0] /Q
D
Q+ Flip-Flop Q- DELAY (ps)
Delay vs. Tap
12000 10000 8000 6000 4000 2000 0 0 200 400 600 800 1000 1200 TAP (DIGITAL WORD)
CK
CONTROL LOGIC
ECL Pro is a registered trademark of Micrel, Inc. M0643-121504
Rev.: C Amendment: /0
1
Issue Date: December 2004
Micrel
ECL Pro(R) SY100EP195V
PACKAGE/ORDERING INFORMATION
D7 D6 D5 D4 VEE D3 D2 D1
Ordering Information
24 23 22 21 20 19 18 17 VEE D0 VCC Q /Q VCC VCC NC
32 31 30 29 28 27 26 25 D8 D9 D10 IN /IN VBB VEF VCF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Part Number SY100EP195VTI SY100EP195VTITR(1)
Note: 1. Tape and Reel.
Package Type T32-1 T32-1
Operating Range Industrial Industrial
Package Marking SY100EP195V SY100EP195V
32-Pin TQFP (T32-1)
FUNCTIONAL BLOCK DIAGRAM
VEE LEN SETMIN SETMAX VCC /CASCADE CASCADE /EN
IN /IN 512 /EN GD
0 1
0 1
0 1
0 1
0 1
256 GD
128 GD
64 GD
32 GD
0 1
0 1
0 1
0 1
0 1
16 GD
8 GD
4 GD
2 GD
1 GD
D[9:0] LEN SETMIN SETMAX 1 GD 10-bit Latch
0 1
Q /Q
D[10]
CASCADE Latch /CASCADE
VBB VCF VEF
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PIN DESCRIPTION
Pin Number 23, 25, 26, 27, 29, 30, 31, 32, 1, 2 Pin Name D[0:9] Pin Function CMOS, ECL, or TTL Select Inputs: These digital control signals adjust the amount of delay from IN to Q. Please refer to the "Ac Electrical Table" (page 7) and Table 7 (page 17) for delay values. Figure 9 shows how to interface these inputs to various logic family standards. These inputs default to logic low when left unconnected. Bit 0 is the least significant bit, and bit 9 is the most significant bit. CMOS, ECL, or TTL Select Input: This input latches just like D[0:9] does. It drives the CASCADE, /CASCADE differential pair. Use only when cascading two or more SY100EP195V to extend the range of delays required. ECL Input: This is the signal to be delayed. If this input pair is left unconnected, this is equivalent to a logic low input. Voltage Output: When using a single-ended logic source for IN and /IN, connect the unused input of the differential pair to this pin. This pin can also re-bias AC-coupled inputs to IN and /IN. When used, de-couple this pin to VCC through an 0.01F capacitor. Limit current sinking or sourcing to 0.5mA or less. Voltage Output: Connect this pin to VCF when the D inputs are ECL. Refer to the "Digital Control Logic Standard" section of the "Functional Description" to interface the D inputs to CMOS or TTL. Voltage Input: The voltage at this pin sets the logic transition threshold for the D inputs. Most Negative Supply: Supply ground for PECL systems. ECL Control Input: When logic low, the D inputs flow through. Any changes to the D inputs reflect in the delay between IN, /IN and Q, /Q. When logic high, the logic values at D are latched, and these latched bits determine the delay. ECL Control Input: When logic high, the contents of the D register are reset. This sets the delay to the minimum possible, equivalent to D[0:9] being set to 0000000000. When logic low, the value of the D register, or the logic value of SETMAX determines the delay from IN, /IN to Q, /Q. This input defaults to logic low when left unconnected. ECL Control Input: When logic high and SETMIN is logic low, the contents of the D register are set high, and the delay is set to one step greater than the maximum possible with D[0:9] set to 1111111111. When logic low, the value of the D register, or the logic value of SETMIN determines the delay from IN, /IN to Q, /Q. This input defaults to logic low when left unconnected. Most Positive Supply: Supply ground for NECL systems. Bypass to VEE with 0.1F and 0.01F low ESR capacitors. 100 ECL Outputs: These outputs are used when cascading two or more SY100EP195V to extend the delay range required. ECL Control Input: When set active low, Q, /Q are a delayed version of IN, /IN. When set inactive high, IN, /IN are gated such that Q, /Q become a differential logic low. This input defaults to logic low when left unconnected. 100k ECL Outputs: This signal pair is the delayed version of IN, /IN. No Connect: Leave this pin unconnected.
3
D[10]
4, 5 6
IN, /IN VBB
7
VEF
8 9, 24, 28 10
VCF VEE LEN
11
SETMIN
12
SETMAX
13, 18, 19, 22 15, 14 16
VCC CASCADE, /CASCADE /EN
20, 21 17
Q, /Q NC
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Absolute Maximum Ratings(1)
Supply Voltage (VCC) PECL Mode (VEE=0V) ............................. -0.5V to +6.0V Supply Voltage (VEE) NECL Mode (VCC=0V) ............................ +0.5V to -6.0V Any Input Voltage (VIN) PECL Mode ....................................... -0.5V to VCC+0.5V NECL Mode ....................................... +0.5V to VEE-0.5V ECL Output Current (IOUT) Continuous ............................................................. 50mA Surge .................................................................... 100mA IBB Sink/Source Current .......................................... 0.5mA Lead Temperature (soldering, 10 sec.) ................... +300C Storage Temperature (TS) ....................... -65C to +150C ESD Rating(3) ........................................................... >1.5kV
Operating Ratings(2)
Supply Voltage (VCC) PECL Mode (VEE=0V) ............................. +3.0V to +5.5V Supply Voltage (VEE) NECL Mode (VCC=0V) ............................ -3.0V to -5.5V Ambient Temperature (TA) ......................... -40C to +85C Package Thermal Resistance TQFP-32 (JA) Still-air ............................................................. 50C/W 500lfpm ............................................................ 42C/W TQFP-32 (JC) ..................................................... 20C/W
DC ELECTRICAL CHARACTERISTICS
TA = -40C to +85C. Symbol VCC VEE IEE
Notes: 1. Permanent device damage may occur if "Absolute Maximum Ratings" are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to "Absolute Maximum Rating" conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Devices are ESD sensitive. Handling precautions recommended. 4. Required 500lfpm air flow when using +5V or -5V power supply.
Parameter Power Supply Voltage (PECL)
Condition
Min 3.0 4.5
Typ 3.3 5.0 -3.3 -5.0 150
Max 3.6 5.5 -3.0 -4.5 175
Units V V V V mA
Power Supply Voltage (NECL)
-3.6 -5.5
Power Supply
Current(4)
No load, over supply voltage
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LVPECL DC ELECTRICAL CHARACTERISTICS (100kEP)
VCC = 3.3V, VEE = 0V; TA = -40C to +85C.(5, 6) Symbol VOH VOL VIH Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage PECL CMOS TTL Input LOW Voltage PECL CMOS TTL Output Voltage Reference Input Select Voltage Mode Connection Input HIGH Voltage Common Mode Range(7) Input HIGH Current Input LOW Current IN /IN 0.5 -150 Figure 5 Condition Figures 2, 3, 6 Figures 2, 3, 6 Figures 1, 4 2075 1815 2000 Figures 1, 4 1355 1675 1485 800 1875 1720 2000 1975 1825 2100 3.3 150 mV mV mV mV mV mV V A A A 2420 mV mV mV Min 2155 1355 Typ 2280 1480 Max 2405 1605 Units mV mV
VIL
VBB VCF VEF VIHCMR IIH IIL
1775 1610 1900 2.0
Notes: 5. Device is guaranteed to meet the DC specifications, shown in the table below, after thermal equilibrium has been established. The device is tested in a socket such that transverse airflow of 500lfpm is maintained. 6. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3V to -2.2V. 7. VIHCMR maximum varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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PECL DC ELECTRICAL CHARACTERISTICS (100kEP)
VCC = 5.0V, VEE = 0V; TA = -40C to +85C.(8, 9) Symbol VOH VOL VIH Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage PECL CMOS TTL Input LOW Voltage PECL CMOS TTL Output Voltage Reference Input HIGH Voltage Common Mode Range(10) Input HIGH Current Input LOW Current IN /IN 0.5 -150 Figure 5 Condition Figures 2, 3, 6 Figures 2, 3, 6 Figures 1, 4 3775 2750 2000 Figures 1, 4 3055 3375 2250 800 3575 3675 5.0 150 mV mV mV mV V A A A 4120 mV mV mV Min 3855 3055 Typ 3980 3180 Max 4105 3305 Units mV mV
VIL
VBB VIHCMR IIH IIL
3475 2.0
NECL DC ELECTRICAL CHARACTERISTICS (100kEP)
VCC = 0V, VEE = -5.5V to -3.0V; TA = -40C to +85C.(8) Symbol VOH VOL VIH VIL VBB VIHCMR IIH IIL Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage NECL Input LOW Voltage NECL Output Voltage Reference Input HIGH Voltage Common Mode Range(11) Input HIGH Current Input LOW Current IN /IN 0.5 -150 Figure 5 Condition Figures 2, 3 Figures 2, 3 Figures 1, 4 Figures 1, 4 Min -1145 -1945 -1225 -1945 -1525 VEE+2.0 -1425 Typ -1020 -1820 Max -895 -1695 -880 -1625 -1325 0.0 150 Units mV mV mV mV mV V A A A
Notes: 8. Device is guaranteed to meet the DC specifications, shown in the table above, after thermal equilibrium has been established. The device is tested in a socket such that transverse airflow of 500lfpm is maintained. 9. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0V to -0.5V. 10. VIHCMR maximum varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 11. VIHCMR minimum varies 1:1 with VEE. The VIHCMR range is referenced to the most positive side of the differential input signal.
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AC ELECTRICAL CHARACTERISTICS
VCC = 3.0 to 5.5V, VEE = 0V or VCC = 0V, VEE = -3.0 to -5.5V; TA = -40C to +85C.(12, 13) TA = -40C Symbol fMAX tPD Parameter Maximum Frequency(14) 1650 9500 1600 300 7850 Propagation Delay IN to Q; D[0-10]=0 IN to Q; D[0-10]=1023 /EN to Q: D[0-10]=0 D10 to CASCADE Programmable Range tPD(max)-tPD(min) Step Delay(15) D0 High D1 High D2 High D3 High D4 High D5 High D6 High D7 High D8 High D9 High Lin tSKEW tS Linearity(16) Duty Cycle Skew(17) tPHL-tPLH Setup Time D to LEN D to IN(18) /EN to IN(19) LEN to D IN to /EN(20) /EN to IN(21) SETMAX to LEN SETMIN to LEN Cycle-to-Cycle Jitter(22) Input Voltage Swing (Differential) Output Rise/Fall Time 20% to 80% (Q) 20% to 80% (CASCADE) 150 200 300 300 200 400 0 140 150 60 250 200 300 300 200 400 25 0 160 170 100 280 500 250 200 0.2 150 800 210 210 <1 1200 300 300 150 200 300 300 200 400 0 180 180 80 300 ps ps ps ps ps ps ps ps ps <1 1200 325 325 psrms mV ps ps 9 25 42 75 142 296 532 1080 2100 4250 10 10 26 42 80 143 300 540 1095 2150 4300 10 10 27 43 81 150 310 565 1140 2250 4500 10 ps ps ps ps ps ps ps ps ps ps %LSB Min Typ 2.5 2000 11500 2150 420 9450 2450 13500 2600 500 1800 9800 1800 325 8200 Max Min TA = +25C Typ 2.5 2050 12200 2300 450 10000 2600 14000 2800 550 1950 10600 2000 325 8850 Max Min TA = +85C Typ 2.5 2250 13300 2500 525 10950 2750 15800 3000 625 Max Unit GHz ps ps ps ps ps
tRANGE t
tH tR
Hold Time Release Time
400 350
200 275 0.2 800 180 180 <1 1200 250 250
400 350
400 350
300 335 0.2 800 230 230
tJIT VPP tr tf
Notes: 12. AC characteristics are guaranteed by design and characterization. 13. Measured using 750mV source, 50% duty cycle clock source, RL = 50 to VCC - 2V. 14. Refer to "Typical Operating Characteristics" for output swing performance. 15. The delays of the individual bits are cumulative. 16. Linearity is the deviation from the ideal delay. 17. Duty cycle skew guaranteed only for differential operation measured from the crosspoint of the input edge to the crosspoint of the corresponding output edge. 18. Setup time defines the amount of time prior to an edge on IN, /IN that the D[0:9] bits must be set to guarantee the new delay will occur for that edge. 19. Setup time is the minimum that /EN must be asserted prior to the next transition of IN, /IN to prevent an output response greater than 75mV to that IN, /IN transition. 20. Hold time is the minimum time that /EN must remain asserted after a negative going IN or a positive going /IN to prevent an output response greater than 75mV to that IN, /IN transition. 21. Release time is the minimum time that /EN must be deasserted prior to the next IN, /IN transition to ensure an output response that meets the specified IN to Q propagation delay and transition times. 22. This is the amount of generated jitter added to an otherwise jitter free clock signal, going from IN, /IN to Q, /Q, where the clock may be any frequency between 0.0 and 2.5GHz.
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TYPICAL OPERATING CHARACTERISTICS
800 700 OUTPUT SWING (mV) 600
Q, /Q Output Swing vs. Frequency
180 160 140
IEE (mA)
Supply Current vs. Temperature
VCC = 5.5V VCC = 3.3V
500 400 300 200 100 0 0 500 1000 1500 2000 2500 3000 FREQUENCY (MHz)
120 V = 5.0V CC 100 80 60 40 20
VCC = 3.0V
0 -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
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ECL Pro(R) SY100EP195V
VCC
VCC
5;-2'#8
75k9
Q, CASCADE
IN
/Q, /CASCADE
/IN
75k9
75k9
SY100EP195V
Figure 1a. Differential Input Structure
VCC
SY100EP195V
Figure 2. Emitter Output Structure
/EN LEN SETMIN SETMAX D[0:10]
Q /Q CASCADE /CASCADE
VOH VOL 0V
VBB
Figure 3a. Output Levels, PECL, LVPECL
75k9
Figure 1b. Single-Ended Input Structure
Q /Q CASCADE /CASCADE
0V VOH VOL
Figure 3b. Output Levels, NECL
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VCC VIH(MAX)
Invalid
0V VIH(MAX)
Invalid
Logic High VIH(MIN) VIL(MAX) Invalid Logic Low VIL(MIN) 0V
VIL(MIN) VEE VIH(MIN) VIL(MAX)
Logic High Invalid Logic Low
Invalid
Invalid
Figure 4a. Input Levels, PECL
Figure 4c. Input Levels, NECL
Invalid VCC Logic High VIH(MIN) VIL(MAX)
IN
VIHCMR
/IN
Invalid
0V
Logic Low 0V Invalid
Figure 5a. Input Common Mode, PECL, LVPECL
Figure 4b. Input Levels, CMOS, TTL
IN
0V VIHCMR
/IN
VIHCMR
Figure 5b. Input Common Mode, NECL
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TERMINATING PECL
+3.3V
+3.3V
ZO = 50 ZO = 50
R1 130
R1 130
+3.3V
R2 82
R2 82
Vt = VCC --2V
Figure 6a. Parallel Termination--Thevenin Equivalent
Note: 1. For +5.0V systems: R1 = 82, R2 = 130.
+3.3V
Z = 50 Z = 50 50 50
+3.3V
Source 50 Rb
Destination C1 (optional) 0.01F
Figure 6b. Three-Resistor "Y-Termination"
Notes: 1. Power-saving alternative to Thevenin termination. 2. Place termination resistors as close to destination inputs as possible. 3. Rb resistor sets the DC bias voltage, equal to Vt. For +3.3V systems Rb = 46 to 50. For +5V systems, Rb = 110.
+3.3V R1 130 ZO = 50
+3.3V R1 130 50
+3.3V
Q
+3.3V
/Q Vt = VCC --2V R2 82 R2 82 0.01F +3.3V
VBB
Figure 6c. Terminating Unused I/O
Notes: 1. Unused output (/Q) must be terminated to balance the output. 2. Micrel's differential I/O logic devices include a VBB reference pin . 3. Connect unused input through 50 to VBB. Bypass with a 0.01F capacitor to VCC, not GND, as PECL is referenced to VCC. M0643-121504
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VCC +3.3V
0.01F PECL Output
ECL Pro(R) SY100EP195V
VCC
LVPECL Signals
D[0:10] VCF
IN /IN VBB
SY100EP195V
VEF
5;-2'#8
VEE 0V
Figure 7a. Interfacing to a Single-Ended PECL Signal
VCC
Figure 9b. Connecting LVPECL Signals to the D Inputs
VCC +3.3V or +5.0V CMOS Inputs
0.01F
D[0:10] NC VCF
IN
PECL Output
/IN
NC VEF
5;-2'#8
5;-2'#8
VBB
VEE 0V
Figure 7b. Interfacing to and Inverting a Single-Ended PECL Signal
Figure 9c. Connecting CMOS Signals to the D Inputs Note: VCF and VEF are not connected.
IN
VCC +3.3V
VCC 50 0.01F 50
/IN
VBB
TTL Inputs
5;-2'#8
D[0:10]
VCF
Figure 8. Re-Biasing an AC-Coupled Signal
1.5k9
NC VEF
SY100EP195V
0V
VEE 0V
VCC +5.0V PECL Signals
D[0:10] VCF VEF
5;-2'#8
Figure 9d. Connecting TTL Signals to the D Inputs, with VCC = 3.3V
VCC +5.0V TTL Inputs
D[0:10] VCF
VEE 0V
Figure 9a. Connecting PECL Signals to the D Inputs
5009 0V
NC VEF
5;-2'#8
VEE 0V
Figure 9e. Connecting TTL Signals to the D Inputs, with VCC = 5.0V
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FUNCTIONAL DESCRIPTION
SY100EP195V is a programmable delay line, varying the delay of a PECL or NECL input signal by any amount between about 2.2ns and 12.2ns. A 10-bit digital control register affords delay steps of approximately 10ps. SY100EP195V implements the delay using a multiplexer chain and a set of fixed delay elements. Under digital control, various subsets of the delay elements are included in the signal chain. To simplify interfacing, the 10-bit digital delay control word interfaces to PECL, CMOS, or TTL interface standards. Since multiplexers must appear in the delay path, SY100EP195V has a minimum delay of about 2.2ns. Delays below this value are not possible. In addition, when cascading multiple SY100EP195V to extend the delay range, the minimum delay is about 2.2ns times the number of SY100EP195V in cascade. An eleventh control bit, D[10], along with the CASCADE and /CASCADE outputs and the SETMIN and SETMAX inputs, simplifies the task of cascading. Signal Path Logic Standard The signal path, from IN, /IN to Q, /Q, interfaces to PECL, LVPECL, or NECL signals, as shown in Table 6. The choice of signal path logic standard may limit possible choices for the delay control inputs, D. Input Enable The /EN input gates the signal at IN, /IN. When disabled, the input is effectively gated out, just as if a logic low was being provided to SY100EP195V.
/EN L H Value at Q, /Q IN, /IN Delayed Logic Low Delayed
Digital Control Logic Standard When used in systems where VEE connects to ground, SY100EP195V may interface either to PECL, CMOS, or TTL on its D[0:10] inputs. To this end, the VCF pin sets the threshold at which the D inputs switch between logic low and logic high. As shown in Table 3, connecting VCF to VEF sets the threshold to PECL (if VCC is 5V) or LVPECL (if VCC is 3.3V). Leaving VCF and VEF open yields a threshold suitable for detecting CMOS output logic levels. Leaving VEF open and connecting VCF to a 1.5V source allows the D inputs to accept TTL signals.
Logic Standard ECL, PECL CMOS TTL VCF Connection VEF No Connect 1.5V Source
Table 3. Digital Control Standard Truth Table If a 1.5V source is not available, connecting VCF to VEE through an appropriate resistor will bias VCF at about 1.5V. The value of this resistor depends on the VCC supply, as indicated in Table 4.
VCC 3.3V 5.0V Resistor Value 1.5k 500
Table 4. Resistor Values for TTL Input Cascade Logic SY100EP195V is designed to ease cascading multiple devices in order to achieve a greater delay range. The SETMIN and SETMAX pins accomplish this, as set out in the applications section below. SETMIN and SETMAX override the delay by changing the value in the D latch register. Table 5 lists the action of these pins.
SETMIN L L H H SETMAX L H L H Nominal Delay (ps) As per D Latch 2200 + 10 x 1024 2200 Not Allowed
Table 1. /EN Truth Table Digital Control Latch SY100EP195V can capture the digital delay control word into its internal 11-bit latch, 10 bits for D[0:9], and an extra bit for the D[10] cascade control. The LEN input controls the action of this latch, as per Table 2. Note that the LEN input is always PECL, LVPECL, or NECL, the same as the IN, /IN signal pair. The 11-bit delay control word, however, may also be CMOS or TTL.
LEN L H Latch Action Pass Through D[0:10] Latch D[0:10]
Table 5. SETMIN and SETMAX Action
Table 2. LEN Truth Table The nominal delay value is based on the binary value in D[0:9], where D[0] is the least significant bit, and D[9] is the most significant bit. This delay from IN, /IN to Q, /Q is about:
t = 2200 + 10 x value(D[9:0]), ps
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Signal Path Logic Standard PECL LVPECL NECL
VCC +4.5V to +5.5V +3.0V to +3.6V 0V
VEE 0V 0V -3.0 to -5.5V
Delay Control Input Choices PECL, CMOS, TTL LVPECL, CMOS, TTL NECL
Table 6. Signal Path Logic Standard
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APPLICATIONS INFORMATION
For best performance, use good high frequency layout techniques, filter VCC supplies, and keep ground connections short. Use multiple vias where possible. Also, use controlled impedance transmission lines to interface with the SY100EP195V data inputs and outputs. VBB Supply The VBB pin is an internally generated supply, and is available for use only by the SY100EP195V. When unused, this pin should be left unconnected. The two common uses for VBB are to handle a single-ended PECL input, and to rebias inputs for AC-coupling applications. If IN, /IN is driven by a single-ended output, VBB is used to bias the unused input. Please refer to Figures 7. The PECL signal driving SY100EP195V may optionally be inverted in this case. When the signal is AC-coupled, VBB is used, as shown in Figure 8, to re-bias IN, /IN. This ensures that SY100EP195V inputs are within its acceptable common mode range. In all cases, VBB current sinking our sourcing must be limited to 0.5mA or less. Setting D Input Logic Thresholds As explained earlier, in all designs where the SY100EP195V VEE supply is at zero volts, the D inputs may accommodate CMOS and TTL level signals, as well as PECL or LVPECL. Figures 9 show how to connect VCF and VEF for all possible cases. Cascading Two or more SY100EP195V may be cascaded, in order to extend the range of delays permitted. Each additional SY100EP195V adds about 2200ps to the minimum delay, and adds another 10240ps to the delay range. Internal cascade circuitry has been included in the SY100EP195V. Using this internal circuitry, SY100EP195V may be cascaded without any external gating. Examples of cascading 2, 3, or 4 SY100EP195V appear in Figures 10. Table 7 lists the nominal delay for all the cases that appear in Figures 10.
Control Word (11bits)
SY100EP195V SY100EP195V
C[10] C[9:0]
#2
D[10] D[9:0]
#1
IN /IN
Q /Q SETMIN SETMAX
IN /IN /CASCADE CASCADE
Q /Q
Figure 10a. Cascading Two SY100EP195V
Control Word (12bits)
SY100EP195V
SY100EP195V
SY100EP195V
C[11]
D[10]
C[10] C[9:0]
D[10] D[9:0]
#1
#3
#2
IN /IN
Q /Q SETMIN SETMAX
IN /IN
Q
IN /IN /CASCADE CASCADE
Q /Q
/Q SETMIN /CASCADE SETMAX CASCADE
Figure 10b. Cascading Three SY100EP195V
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Control Word (12bits)
SY100EP195V
SY100EP195V
SY100EP195V
SY100EP195V
C[11]
D[10]
C[10] C[9:0]
D[10] D[9:0] IN /IN /CASCADE CASCADE Q /Q
IN /IN
Q /Q SETMIN SETMAX
IN /IN
Q /Q SETMIN SETMAX
IN /IN
Q
/Q SETMIN /CASCADE SETMAX CASCADE
Figure 10c. Cascading Four SY100EP195V
RELATED PRODUCT AND SUPPORT DOCUMENTATION
Part Number SY100EP196VTI SY55856UHI Function 3.3V/5V Programmable Delay Chip with Fine Tune Control 2.5V/3.3V 2.5GHz Differential 2-Channel Precision CML Delay Line Data Sheet Link http://www.micrel.com/product-info/products/sy100ep196v.shtml http://www.micrel.com/product-info/products/sy55856u.shtml
M0643-121504
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Micrel Control Inputs D[10] 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 Nominal Delay (ps) Two Chips Three Chips 4,400 6,600 4,410 6,610 4,420 6,620 4,440 6,640 4,480 6,680 4,560 6,760 4,720 6,920 5,040 7,240 5,680 7,880 6,960 9,160 9,520 11,720 14,630 16,830 14,640 16,840 14,650 16,850 14,660 16,860 14,680 16,880 14,720 16,920 14,800 17,000 14,960 17,160 15,280 17,480 15,920 18,120 17,200 19,400 19,760 21,960 24,870 27,070 27,080 27,090 27,100 27,120 27,160 27,240 27,400 27,720 28,360 29,640 32,200 37,310 27,080 27,090 27,100 27,120 27,160 27,240 27,400 27,720 28,360 29,640 32,200 37,310
ECL Pro(R) SY100EP195V
D[11] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
D[9:0] 0000000000 0000000001 0000000010 0000000100 0000001000 0000010000 0000100000 0001000000 0010000000 0100000000 1000000000 1111111111 0000000000 0000000001 0000000010 0000000100 0000001000 0000010000 0000100000 0001000000 0010000000 0100000000 1000000000 1111111111 0000000000 0000000001 0000000010 0000000100 0000001000 0000010000 0000100000 0001000000 0010000000 0100000000 1000000000 1111111111 0000000000 0000000001 0000000010 0000000100 0000001000 0000010000 0000100000 0001000000 0010000000 0100000000 1000000000 1111111111
One Chip 2,200 2,210 2,220 2,240 2,280 2,360 2,520 2,840 3,480 4,760 7,320 12,430
Four Chips 8,800 8,810 8,820 8,840 8,880 8,960 9,120 9,440 10,080 11,360 13,920 19,030 19,040 19,050 19,060 19,080 19,120 19,200 19,360 19,680 20,320 21,600 24,160 29,270 29,280 29,290 29,300 29,320 29,360 29,440 29,600 29,920 30,560 31,840 34,400 39,510 39,520 39,530 39,540 39,560 39,600 39,680 39,840 40,160 40,800 42,080 44,640 49,750
Table 7. List of Nominal Delay Values for Cascaded SY100EP195V
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Micrel
ECL Pro(R) SY100EP195V
32 LEAD TQFP (T32-1)
Rev. 01
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131
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+ 1 (408) 944-0800
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The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2004 Micrel, Incorporated. M0643-121504
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